New Method Stacks Silicon Circuits for 3D Chips

Researchers have developed a new method for stacking silicon circuits in multiple layers. This process could increase computing power and extend Moore's Law. The technique uses ultra-thin silicon membranes and low-temperature manufacturing. This overcomes a major obstacle in producing true three-dimensional (3D) chips.

For decades, computing power increased by miniaturizing transistors on a single chip. This trend, known as Moore's Law, is reaching physical limits. Building upward by stacking circuits offers an alternative. A team at the University of Illinois Grainger College of Engineering demonstrated this new stacking method. It could significantly increase computing density, improve performance, and reduce energy consumption.

The new process achieves high device yields, between 98% and 100%. It uses standard single-crystalline silicon. This material is the foundation of modern electronics. The method allows for monolithic integration, where each new device layer is fabricated directly on top of the previous one. This creates much denser vertical connections and shorter distances between layers.

A key challenge for monolithic integration has been high temperatures. Fabricating high-quality silicon devices typically requires temperatures near 1,000 degrees Celsius. Such heat would damage existing metal interconnects in lower layers. The Illinois team's method uses ultra-thin freestanding silicon nanomembranes. These membranes are transferred at temperatures no higher than 200 degrees Celsius. This preserves the crystalline quality of the silicon while staying within thermal limits.

The researchers also redesigned the transistor architecture. They used junctionless transistors, which are uniformly and heavily doped before stacking. This avoids high-temperature doping processes. The team fabricated three stacked layers, each containing 625 transistors. These devices showed strong uniformity and high manufacturing yield. Their performance matched conventional silicon transistors made at much higher temperatures.

The process is scalable beyond the three layers demonstrated. It yields high-performing transistors with low variability. The work was supported by the National Science Foundation and industry partners. The team plans to transfer this technology to an industrial semiconductor foundry. This is a step toward commercial production of monolithic 3D silicon chips.